(a) Field of the Invention
The present invention relates to a load-less four-transistor memory cell and a method for fabricating the same. More particularly, the present invention relates to a memory cell in a semiconductor memory device which is capable of realizing a stable and high-speed memory cell operation, and which can be suitably used as a SRAM (Static Random Access Memory).
(b) Description of the Related Art
Semiconductor memory devices are generally classified into three types including DRAMs (Dynamic Random Access Memories), SRAMs, and ROMs (Read Only Memories).
In a DRAM, each memory cell is composed of two elements, i.e., a MIS (Metal Insulator Semiconductor) transistor, such as MOS (Metal Oxide Semiconductor) transistor, and a storage capacitor. Therefore, a DRAM has advantages such as a high degree of integration and a high cost performance.
A SRAM, on the other hand, has advantages such as a high operating speed and a lower power dissipation as compared to the DRAM. However, in a SRAM, each memory cell is typically composed of six transistors, or four transistors and two resistive loads. Thus, it has be considered that a SRAM is not suitable for realizing a high degree of integration due to such a large number of elements per memory cell.
Basically, a SRAM includes a flip flop circuit or latch circuit and a pair of access transistors connected to the flip flop circuit, and the flip flop circuit is typically a combination of two inverter circuits connected in a positive feed-back loop.
An inverter circuit can be obtained as either a combination of an N-channel MOS transistor (referred to as an xe2x80x9cNMOS transistorxe2x80x9d) and a P-channel MOS transistor (referred to as a xe2x80x9cPMOS transistorxe2x80x9d), or a combination of an NMOS transistor and a resistive load.
A memory cell of a SRAM including six transistors is called a xe2x80x9cfull-CMOS memory cellxe2x80x9d because the transistors are CMOS transistors, and is called herein full-CMOS six-transistor memory cell. This type of SRAM is the largest among various types of SRAMs in terms of the area occupied by a single memory cell.
On the other hand, a memory cell of a SRAM including four transistors and two resistive loads uses MOS transistors while providing the resistive loads above the MOS transistors, thereby reducing the total area to be occupied by the six elements. Therefore, the area required for one memory cell is smaller than that of a six-transistor memory cell.
However, production of the memory cell having resistive loads, as compared to that of a six-transistor memory cell, requires additional fabrication steps for forming the resistive loads because the resistive loads are generally formed on a polycrystalline silicon film.
It is also necessary to connect those elements with one another, thereby complicating the structure of the memory cell. Moreover, it is believed that it is more difficult to realize a low-voltage operation by the memory cell having the resistive loads compared to the full-CMOS six-transistor memory cell due to a large time constant of the resistive loads.
In recent years, there is a particular demand in the market for a SRAM capable of operating at a lower source voltage, i.e., at a low power dissipation. Accordingly, full-CMOS memory cells are more widely used than the memory cells having resistive loads despite of their smaller chip area.
Recently, a SRAM using full-CMOS memory cells that only require four transistors and do not have any resistive load was if proposed in the art, as described in Japanese Patent Laid-Open Publication Nos. 7-302847 and 6-104405. This type of memory cell is called hereinafter load-less four-transistor memory cell (full-CMOS four transistor) memory cell, or simply four-transistor memory cell.
Such a load-less four-transistor memory cell includes a pair of drive transistors (NMOS transistors) and a pair of access transistors (PMOS transistors), wherein no load element is connected to the storage node of the drive transistor.
The structure and the operation of the conventional six-transistor memory cell and those of the conventional four-transistor memory cell will now be described in detail with reference to FIGS. 1A, 1B, 2A and 2B. FIGS. 1A and 1B are circuit diagrams illustrating the full-CMOS six-transistor memory cell and the load-less four-transistor memory cell, respectively, and FIGS. 2A and 2B are diagrams illustrating the operations of the six-transistor memory cell and the four-transistor memory cell, respectively.
As illustrated in FIG. 1A, the six-transistor memory cell includes a total of six transistors, i.e., a pair of drive transistors N11 and N12 (NMOS transistors), a pair of load transistors P11 and P12 (PMOS transistors), and a pair of access transistors or transfer transistors N13 and N14 (NMOS transistors).
The six-transistor memory cell operates as follows during a data retaining operation or a standby mode. As illustrated in FIG. 2A, the drive transistor N11 and the access transistor N13 are OFF whereas the load transistor P11 is ON to maintain the storage node 11 at a high level, after data xe2x80x9c1xe2x80x9d is written to the six-transistor memory cell.
In this state, if the load transistor P11 were OFF, the storage node 11 gradually loses its charge, thereby lowering the potential thereof, due to a junction leakage current or a leakage current through the drive transistor N11. The potential of the storage node 11 is maintained at the high level due to the charge by a current flowing from the Vcc source line via the load transistor P11.
When the access transistor N13 is turned ON following the state as described above, a current flows from the storage node 11 to the digit line D11, thereby allowing the stored data to be read out to the digit lines or signal lines.
Next, the configuration and the operation of the load-less four-transistor memory cell will be described. As illustrated in FIG. 1B, the load-less four-transistor memory cell includes a total of four transistors, i.e., a pair of drive transistors N15 and N16 (NMOS transistors), and a pair of access transistors P13 and P14 (PMOS transistors). A major difference between the load-less four-transistor memory cell and the six-transistor memory cell, beside the difference in the number of elements, is that the access transistors P13 and P14 of the load-less four-transistor memory cell are PMOS transistors and supplies leakage current therethrough.
More specifically, the load-less four-transistor memory cell operates as follows during a data retaining operation. As illustrated in FIG. 2B, the drive transistor N15 and the access transistor P13 are OFF when the storage node 13 is at a high level, i.e., after data xe2x80x9c1xe2x80x9d is written to the load-less four-transistor memory cell.
In this state, without the leakage current through the access transistor P13, as stated in the case of the six-transistor memory cell, the potential of the storage node 13 gradually decreases due to a junction leakage current or a leakage current through the drive transistor N15. While the load-less four-transistor memory cell has no dedicated load element for supplying a current to the storage node 13, the OFF-current (or junction leakage current) of the access transistor P13 flows to the storage node 13 to thereby compensate for the charge loss from the storage node 13.
When the access transistor P13 is turned ON after the state as described above, a current flows from the storage node 13 to the digit line D13, thereby allowing the stored data to be read out.
In order for the load-less four-transistor memory cell to operate, it is necessary that the OFF-current (leakage current) of the access transistor P13 or P14 (PMOS transistor) is greater than the OFF-current of the drive transistor N15 or N16 (NMOS transistor).
An advantage of the load-less four-transistor memory cell is that it eliminates the need for providing load elements that are generally connected to the storage nodes of the drive transistors, thereby simplifying the structure of the memory cell.
Next, the structure of the conventional load-less four-transistor memory cell will be described in more detail with reference to FIGS. 3 and 4. FIG. 3 is a top plan view of the conventional load-less four-transistor memory cell, and FIG. 4 is a sectional view of the conventional load-less four-transistor memory cell taken along line A-Axe2x80x2 of FIG. 3.
As illustrated in FIG. 4, the conventional load-less four-transistor memory cell includes a pair of drive transistors N15 and N16 having a pair of storage nodes 13 and 14, and a pair of access transistors P13 and P14 for connecting the digit lines D13 and D14 to the storage nodes 13 and 14.
The drain of the access transistor P13 is connected to the storage node 13, and is further connected to the gate electrode 20 of the drive transistor N15 via the storage node 13. The diffused region (drain) of the drive transistor N15 is connected to the gate electrode of the drive transistor N16 whereas the diffused region (drain) of the drive transistor N16 is connected to the gate electrode of the drive transistor N15 and to the storage node 14.
Next, a method for fabricating the conventional load-less four-transistor memory cell will be described with reference to FIGS. 5A to 5E, which show, at the section along line A-Axe2x80x2 of FIG. 3, consecutive steps of fabrication of the conventional load-less four-transistor memory cell.
First, as illustrated in FIG. 5A, a device isolation trench 21 is formed in a predetermined region of a semiconductor substrate 20 by using a conventional selective oxidization method or a trench isolation technique. Subsequently, a gate insulation film 22 made of silicon oxide (SiO2) is formed in a region other than the device isolation trench 21 by using an oxidization technique.
Then, as illustrated in FIG. 5B, gate electrodes 18 and 19 are formed in predetermined locations by using a CVD technique and a photolithographic technique. A well formation step or an ion injection step for controlling the threshold voltage of the transistor may be performed prior to the gate electrode formation step.
Then, as illustrated in FIG. 5C, an interlayer dielectric film 24, e.g., an oxide film, is formed across the entire surface of the semiconductor substrate 20, and contact holes 25 are formed at predetermined positions by a photolithographic technique and an etching technique.
Then, as illustrated in FIG. 5D, contact plugs 26 are formed in the contact holes 25 by using a CVD technique and an etching technique.
Finally, as illustrated in FIG. 5E, an interconnect layer 27 is formed, thereby completing a sequence of fabrication steps.
As for the connection among the various elements, one or more additional wiring layers may optionally be formed so as to provide multi-layer interconnection structure.
The four-transistor memory cell described in Japanese Patent Laid-Open Publication No. 6-104405 eliminates the need for provision of the resistive loads. In order to hold the data stored in the memory cell, an intermediate potential is applied to the gate of the access transistor so that the access transistor operates as a load resistance during a standby mode of the memory cell. This is achieved by intentionally increasing the OFF-current of the access transistor.
In Japanese Patent Laid-Open Publication No. 10-346149, the threshold voltage of the drive transistor is set to be greater than the absolute value of the threshold voltage of the access transistor so as to enable an excellent cell operation during the standby mode. This is because the magnitude of the OFF-current (leakage current) of the drive transistor, or a typical transistor, varies in reverse proportion to the threshold voltage. In other words, the greater the threshold voltage, the smaller the OFF-current flowing from the storage node of the memory cell.
In the conventional load-less four-transistor memory cell, the access transistor used as a load transistor causes some restrictions on the operation of the memory cell, as detailed below.
It is generally known that a so-called xe2x80x9ccell ratioxe2x80x9d, i.e., the current driveability ratio between the drive transistor and the access MOS transistor, should be higher for achieving the operational stability of a memory cell. The cell ratio is generally expressed by the current driveability of the drive transistor divided by the current driveability of the access transistor.
The reduction in the threshold voltage of the access transistor (which causes an increase in the current driveability therefor) in the load-less four-transistor memory cell as described above results in an increase in the threshold voltage of the drive transistor (i.e., a reduction in the current driveability therefor). This decreases the cell ratio. The current driveability as used herein means the magnitude of the ON-current of the transistor.
In order to avoid the reduction of the cell ratio, the current driveability of the access transistor may be reduced by, for example, reducing the width thereof, or the current driveability of the drive transistor may be increased by, for example, increasing the transistor width thereof.
However, if the current driveability of the access transistor is reduced, it will be difficult to achieve a high-speed operation. On the other hand, if the width of the drive transistor is increased, the memory cell area will be increased.
In view of the above problems in the four-transistor memory cell of the conventional memory device, it is an object of the present invention to provide a memory cell, used in a semiconductor memory device, having four-transistor, which is capable of realizing a stable and high-speed operation of the memory cell, while eliminating the need for providing resistive load elements in the memory cell and without increasing the size of the memory cell.
The present invention provides, in a first aspect thereof, a memory cell in a semiconductor memory device, including a pair of drive MIS transistors having a first conductivity type, the drive MIS transistors forming a data latch for storing data on a pair of storage nodes, and a pair of access MIS transistors having a second conductivity type, the access MIS transistors responding to an access signal to transfer data between the data storage nodes and a pair of signal lines, each of the drive MIS transistors including a first gate insulation film having a thickness smaller than a thickness of a second gate insulation film of each of the access MIS transistors.
The present invention also provides, in a second aspect thereof, a method for forming a memory cell having a pair of drive MIS transistors having a first conductivity type and a pair of access MIS transistors having a second conductivity type, the method comprising the steps of: separating a region of a semiconductor substrate into a plurality of device areas, forming a first gate insulation film on the device areas, selectively removing the first gate insulation film from some of the device areas, forming a second insulation film on the gate first insulation film and on the some of the device areas, and forming the drive MIS transistors each having a gate on the second gate insulation film and the access MIS transistors each having a gate on a combination of the first and second gate insulation films.
In accordance with the memory cell of the present invention and the memory cell fabricated by the method of the present invention, since the drive transistors have gate insulation films having smaller thickness compared to the gate insulation films of the access transistors, it is possible to realize a stable and high-speed memory cell operation while eliminating the need for load elements, without increasing the memory cell size.